The Research Association for Advanced Systems (Members: University of Tokyo, ADVANTEST, Toppan, Hitachi, MIRISE Technologies, RIKEN) Launches the Research and Development of a Next-Generation Advanced Semiconductor Design Platform for the Democratization of Chip Design.
PDF

Professor Suga, an advisor of RaaS and professor emeritus at the University of Tokyo, gave an invited talk on "Surface-activated Room-temperature Bonding as An Advanced 3D Integration Technology" at the 28th Workshop on Electron Device Interface Technology – Physics of Materials, Processes, and Device Characteristics (sponsored by Japan Society of Applied Physics).

The talk provided an overview of surface-activated bonding technology as an advanced 3D integration technology, and introduced the WoW integration technology using low-temperature hybrid bonding that is being developed by RaaS under a NEDO project.
Workshop on Electron Device Interface Technology

RaaS presented on "Trends in Advanced Packaging Technology and Policy Recommendations" at the JEITA Scene-Oriented Advanced Implementation Technology Subcommittee Meeting.

As a member of the 2021 NEDO Advanced Packaging Technology Survey Committee, RaaS surveyed and analyzed related technologies, market trends, and information and communication-related policies, and made recommendations for strengthening Japan’s industrial competitiveness. In addition to reporting on the activities of the same committee, the presentation provided an overview of the latest developments in 3D system integration technology from the perspective of process technology. It also introduced the WoW and CoW integration technology using low-temperature hybrid bonding that RaaS is working on under a NEDO project, and discussed policies to strengthen the competitiveness of Japan's semiconductor industry.

RaaS participated in a poster session at SEMICON Japan/APCS 2022 held at Tokyo Big Sight.

RaaS participated in a poster session at the Advanced Packaging and Chiplet Summit (APCS), a large-scale event for semiconductor packaging and implementation technology that was held for the first time at SEMICON Japan in 2022. The poster described both RaaS's system-track and technology-track activities. We were approached by both university and corporate attendees that allowed us to introduce our activities and engage in technical discussions.

RaaS presented on "Post-5G Project Efforts at The Research Association for Advanced Systems (RaaS)" at the IEEE EPS Japan Evening Meeting.

Advancements in both process scaling technology and advanced packaging technology that integrates peripheral devices such as chiplets into a single package are essential for post-5G information and communication systems. This presentation provided a look at the forefront of 3D system integration technology development including imec’s backside power delivery network (PDN) and AMD’s 3D-Chiplet technologies from a process technology perspective, along with an introduction of the low-temperature hybrid bonding-based WoW and CoW integration technology that is being developed under a NEDO project.
IEEE EPS Japan Chapter Japanese (ieee-jp.org)

RaaS presented an "Introduction of Advanced Packaging-Related Activities" at the JEITA Advanced Packaging Committee Meeting.

In order to realize post-5G information and communication systems, RaaS has been working on 3D system integration from both system design and process technology perspectives. This presentation provided an overview of the forefront of 3D system integration technology development from the perspective of process technology, and introduced the WoW and CoW integration technology using low-temperature hybrid bonding that is being developed in a NEDO project. Our goal is to promote efforts towards the revitalization of Japan's semiconductor industry.

RaaS presented on "Advanced Semiconductor Manufacturing (Backend) Process Technology Development" in a panel discussion at the Opening Symposium of the Advanced Semiconductor Manufacturing Technology Tsukuba Innovation Hub.

The presentation outlined the objectives, overview, and organizational structure of our equipment and process development plan targeting WoW and CoW integration in the development of direct bonding 3D stacking technology.
Opening Symposium; The International innovation hub in Tsukuba toward the advanced semiconductor manufacturing

Proposal from RaaS has been selected by Japan’s Ministry of Economy, Trade and Industry (METI) for its “Project for Research and Development of Enhanced Infrastructures for Post 5G Information and Communications Systems / Development of Advanced Semiconductor Manufacturing Technology (Subsidized).”

Commercial services based on fifth-generation mobile telecommunications systems (5G), the successor to fourth-generation systems (4G), are being initiated around the world. Meanwhile, with further upgrades including ultra-low latency and support for massive simultaneous connections, the next generation technology (Post 5G) is expected to be widely adopted for industrial applications such as smart factory and automated driving. As a result, its successful development can provide Japan with a core competitive advantage. The goal of our proposal is to strengthen Japan’s development and manufacturing infrastructures for Post 5G information and communications systems through the development of manufacturing technology for advanced semiconductors demanded by such systems.

The University of Tokyo, Toppan Inc., Panasonic Corporation, Hitachi Ltd., and MIRISE Technologies jointly established the Research Association for Advanced Systems (RaaS) on Aug 17, 2020, with Professor Tadahiro Kuroda, Director of Systems Design Lab at the Graduate School of Engineering, University of Tokyo, serving as its chairperson.

RaaS pursues the development of a design platform for the specialized chips required to create systems demanded by a data-driven society. It targets a 10-fold increase in development efficiency of specialized chips through the deployment of open architecture. In addition, it aims to improve energy efficiency 10-fold by developing 3D integration technology to realize integration of multiple chips manufactured using the latest 7nm CMOS process in the same package.